![]() VTOR is set to 0x00000000 Stack is at the top of DTCM. ![]() The increase of speed is verified by some simple fiducial (pins written up/down) verify. I copy all code (< 16 kB) from flash down to 0x00000000 right after boot, and then I adjust PC to suit. I'm seeing well over twice the delay that I should according to the specs.ΔΆ00 MHz? That is what I set up with the PLL clocking, and that is what is confirmed by running any of the clocks directly to output pins. I think that there is extra "junk" happening in microcode setting up the context saving. ISR is ***supposed*** to take 12 cycles.that is what I read, and what I planned on when writing the code, but not what I see. How do I observe? I poke unused pins at entry and exit of interrupt handler, (and at crucial points in non-interrupt code) and look at them on a scope. I'm reverting to doing it all in low-code, polled, but I hate the jitter that gives me on response to pin edges. So - can I "subvert" the context switching in hardware, and just have it leap to the handler at elevated priority, pausing only to fill the pipeline, and leaving me to take care of stacking what is needed? I don't think so, and haven't seen a way to do it, but I'm working on an extremely tight time-sensitive realtime code, and interrupt switching is eating all my time budget. I am still learning about these, used to the old ARM7 where you had to do it all yourself, however, in those chips, if you had a minimal handler you didn't need to stack much. I am finding (STM32F730Z8, 200 MHz clock, all code including handlers in ITCM, everything in GNU assembly) that it takes about 120-150 ns overhead to get into an interrupt. ![]() The STM32 family has fantastic interrupt service, they stack a whole slew of extra registers for you, and load the LR with an artificial return to properly unstack while looking for opportunities for tail chaining, aborted entry, etc etc. ![]()
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